Ideally, when either a comparator or an operational amplifier (op-amp) has zero volts differential voltage at its inputs it should not produce an amplified signal at its output. In an amplifier, the output should be exactly zero volts, and in a comparator, the output voltage should represent an indeterminate state between its binary logic levels of "zero" and "one". In practicable embodiments, however, sources of error inherent in such devices actually produce an amplified output, which is referred to as the "output offset voltage". The equivalent input voltage which would produce such an output is referred to as the "input offset voltage". Auto-zeroing techniques, used to cancel offset error voltages in comparators and operational amplifiers, are typically implemented as feedback loops around the amplifier and/or comparator that subtract the input offset voltage from the amplifier and/or comparator input voltage.
An implementation of the auto-zeroing technique which is frequently used in analog/digital (A/D) converters fabricated by CMOS processes includes complementary analog switches that are alternately switched on parallel circuit legs by phase-opposed and non-overlapping clocking signals to charge an input capacitor in series therewith repetitively alternatively to the potential of a reference D.C. voltage applied to one of the switches in a D.C. input signal path and to the potential of an input A.C. signal to be A/D converted applied to the other one of the switches in an A.C. input signal path. A single-input, single-output analog inverter, capacitively coupled by the input capacitor to the D.C. reference voltage and to the input A.C. signal via the switches in the D.C. and A.C. signal paths, has an analog switch in a feedback loop between its output and its input that is switched by the same clocking signal that controls the switch that applies the reference D.C. voltage to the input capacitor. The output is coupled to the "D" terminal of a latch, which latch is again clocked by the same clocking signal that applies the reference D.C. voltage to the input capacitor. During auto-zeroing, feedback is applied to one terminal of the input capacitor by the switch in the feedback loop while the other terminal is charged to the reference D.C. voltage by the switch in the D.C. input signal path. Simultaneous to the auto-zeroing, the result of the previous comparison is stored in the latch, which has its "D" input held on the rising edge of the same clocking signal.
The utility of the heretofore known auto-zeroing technique used in analog/digital converters fabricated in CMOS processes is limited both with respect to the speed with which the sampling of the reference D.C. voltage and the input A.C. signals may be accomplished and with respect to the power that is dissipated by the analog inverter (comparator) in the auto-zeroing mode.
The speed is limited on the one hand by the time constant of the input capacitor as it is cyclically caused to sample the reference D.C. voltage and the input A.C. signal alternately applied thereto by the complementary analog switches that are switched in non-overlapping phase-opposition in the D.C. and A.C. input signal paths. Since each latched result requires a sample both of the reference D.C. voltage and of the input A.C. signal on the input capacitor, sufficient time must be allowed to elapse to enable the input capacitor to charge-up during each sampling interval.
The speed is limited on the other hand by transients that are induced on the input capacitor as it is caused to alternately sample the D.C. reference voltage and the A.C. input signal cycle-to-cycle. As charge is supplied to the input capacitor by the input voltage sources sampled at the clock rate, the input voltage sources, which include signal generators and associated impedances, attempt to change their voltage amplitude as soon as the phase-opposed non-overlapping clocking signals turn the several switches "on" and "off" at the clocking rate. Transients are thereby produced which can corrupt the signals being sampled as well as increase the overall noise levels, which transients consequently must be allowed to die-out cycle-to-cycle, placing thereby another limit on the overall achievable speed of the A/D process.
The principal portion of the power is consumed by the analog inverter in its "on" state. Because the analog inverter is switched "on" cycle-to-cycle at the clocking rate, the heretofore known auto-zeroing technique exhibits an undesireably large power consumption, with all its attendant disadvantages.